The VMIVME-7740 VMEbus interface is provided by the PCI-to-VMEbus bridge built around the Tundra Semiconductor Corporation Universe II VMEbus interface chip. The Universe II provides a reliable high-performance 64-bit VMEbus-to-PCI interface in one design. The functions and programming of the Universe-based VMEbus interface are addressed in detail in a separate associated manual titled: VMIVME-7740 Tundra Universe II Based VMEbus Interface Product Manual (500-657740-001).

The VMIACC-5595 is a manageable hub designed for use with GE Fanuc Embedded Systems' VMIxxx-5565 series of reflective memory real-time networking products. The reflective memory hub automatically bypasses ports when signal loss or loss of valid synchronization mode is detected, ensuring the proper functioning of other nodes in the network. Because the optical ports use Small Form-Pluggable (SFP) transceivers, only the required ports need to be installed. The VMIACC-5595's SFP transceivers can be a combination of multimode (short-range) or single-mode (long-range) transceivers. This feature helps save costs and optimize the system in small networks. For large networks, multiple VMIACC-5595 components can be cascaded to build manageable hub arrays with up to 256 nodes. Each port regenerates the serial optical signal, eliminating issues such as insertion loss and cable attenuation. Signal regeneration also reduces jitter. An RS232 port allows you to monitor and control the reflective memory network via a simple PC serial port. Ethernet port functionality allows you to monitor and control the hub remotely via a local area network (LAN) or a web browser.

GENERAL DESCRIPTION — The VMIVME-3115 is a high throughput ,12-bit Analog Input/Output (AIO) board which provides four analog inputs, two analog outputs, and dual 8-bit bi-directional digital input/output ports for VMEbus system applications. Dual-ported data memory, on-board timers, and a program-controlled bus interrupter enables the VMIVME-3115 board to support extensive analog input and output traffic with minimum involvement of the host processor.